A closer look at security verification for RISC-V processors
By Ashish Darbari, Axiomise
EDN (February 13, 2023)
Verifying the security of processors has become an essential step in the design of modern electronic systems. Users want to be sure that their consumer devices can’t be hacked, and that their personal and financial data is safe in the cloud. Effective security verification involves the processor hardware and the many layers of software running atop it.
This article discusses some of the challenges associated with hardware security verification and presents a formal-based methodology to provide a solution. Examples of designs implementing the popular RISC-V instruction set architecture (ISA) demonstrate the power of this approach.
To read the full article, click here
Related Semiconductor IP
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- All-In-One RISC-V NPU
- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
Related White Papers
- Efficient Verification of RISC-V processors
- Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS