A closer look at security verification for RISC-V processors
By Ashish Darbari, Axiomise
EDN (February 13, 2023)
Verifying the security of processors has become an essential step in the design of modern electronic systems. Users want to be sure that their consumer devices can’t be hacked, and that their personal and financial data is safe in the cloud. Effective security verification involves the processor hardware and the many layers of software running atop it.
This article discusses some of the challenges associated with hardware security verification and presents a formal-based methodology to provide a solution. Examples of designs implementing the popular RISC-V instruction set architecture (ISA) demonstrate the power of this approach.
To read the full article, click here
Related Semiconductor IP
- RISC-V IOPMP IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Tiny, Ultra-Low-Power Embedded RISC-V Processor
Related Articles
- Efficient Verification of RISC-V processors
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
Latest Articles
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks