Addressing MIPI M-PHY connectivity challenges for more efficient testing
Chris Loberg, Tektronix
embedded.com (September 20, 2014)
As the industry moves to adopt the MIPI Alliance's M-PHY standard, designers are encountering some significant challenges related to oscilloscope measurements and, more specifically, probing. These challenges include strict requirements such as bus termination and input return loss, as well as the need to minimize common mode loading on the device under test (DUT) and signal fidelity requirements such as wide bandwidth, low noise, and high sensitivity.
The intent of this article is to provide information that will increase your chances of accurate and repeatable test results to ensure compliance with the standard. We will first review the requirements of the M-PHY standard relevant to oscilloscope probing, discuss the tests required in the M-PHY Physical Layer Conformance Test Suite (CTS), and provide practical examples of M-PHY probing with currently available oscilloscopes and probes.
To read the full article, click here
Related Semiconductor IP
- MIPI M-PHY
- MIPI M-PHY HS Gear 4 IP
- MIPI M-PHY IP
- MIPI M-PHY Verification IP
- Simulation VIP for MIPI M-PHY
Related White Papers
- Understand and perform testing for MIPI M-PHY compliance
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- Shift Left for More Efficient Block Design and Chip Integration
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
Latest White Papers
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- How Mature-Technology ASICs Can Give You the Edge
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY