Thalia Design Automation announces AMALIA Platform release 25.3 qualified for advanced process nodes down to 4nm

Platform qualification for sub-10nm semiconductor processes enables tier-1 customers to address next-generation analog and mixed-signal designs with breakthrough intelligent auto-routing capabilities

Cwmbran, United Kingdom – November 4, 2025 – Thalia Design Automation, a leading innovator in electronic design automation (EDA) solutions, today announced the release of AMALIA Platform version 25.3, now qualified for advanced semiconductor process technologies down to 4nm. This milestone qualification enables the platform to support cutting-edge FinFET and advanced node designs, positioning Thalia as a critical solution provider for tier-1, fabless semiconductor companies and leading foundries developing next-generation products. The release also introduces groundbreaking intelligent auto-routing capabilities and enhanced device modeling tools that address critical challenges in process node migration and high-frequency circuit development.

Platform qualification for sub-10nm process technologies

The qualification of AMALIA Platform 25.3 for process nodes down to 4nm represents a strategic advancement for Thalia Design Automation, enabling the company to serve customers designing at the most advanced semiconductor process technologies available today. This capability is essential for analog and mixed-signal IP development in applications including 5G/6G communications, advanced automotive systems, artificial intelligence accelerators and high-performance computing platforms.

"Achieving qualification for 4nm process technology is a defining moment for Thalia Design Automation," said Sowmyan Rajagopalan, CEO, Thalia. "This positions AMALIA as the only specialized full flow, analog and mixed-signal IC migration platform capable of addressing the extreme complexity and precision requirements of sub-10nm designs. Our customers can now leverage our intelligent automation capabilities across the full spectrum of modern semiconductor processes, from mature nodes to the most advanced technologies in production."

The sub-10nm qualification enables AMALIA users to work with the advanced FinFET used by leading foundries. This capability is particularly critical for analog and RF circuit blocks that must be integrated into large system-on-chip (SoC) designs fabricated at advanced nodes.

Breakthrough intelligent auto-routing algorithm

The centerpiece of AMALIA Platform 25.3 is a revolutionary auto-routing algorithm integrated with Layout versus Layout (LVL) comparison capabilities. This intelligent system automatically resolves open and short circuit issues that commonly occur during layout migration between different process design kits (PDKs), dramatically reducing manual intervention and design cycle time.

"The development of this intelligent auto-routing capability represents a fundamental advancement in layout automation," said Awadh Pandey, Thalia’s Director of Engineering. "Our algorithm doesn't just identify connectivity issues – it intelligently resolves them by finding optimal routing paths while avoiding design rule violations and maintaining signal integrity."

The auto-routing system addresses the common challenge where P-cell size changes during PDK migration cause connectivity disruptions. Traditional approaches require manual intervention to reconnect nets, a process that can take weeks for complex analog blocks. The AMALIA 25.3 solution automatically recognizes disconnected nets, identifies the optimal reconnection strategy, and implements the routing while avoiding shorts with adjacent metal layers.

Real-world validation and efficiency gains

The auto-routing development was driven by real-world customer challenges, including a complex bandgap reference design migration that previously required four weeks of manual layout engineering effort. With AMALIA 25.3's intelligent auto-routing, similar migrations can be completed with minimal manual intervention, delivering efficiency improvements of 75% or more compared to traditional manual approaches.

Advanced ‘Safe Operating Area’ analysis

AMALIA Platform 25.3 introduces comprehensive Safe Operating Area (SOA) analysis capabilities within the Technology Analyzer module. This feature extracts critical device reliability parameters directly from PDK model files, including maximum drain-to-gate, gate-to-source, and bulk-to-drain voltages. The SOA data is automatically incorporated into summary reports, providing designers with essential reliability information for robust circuit design.

Enhanced ‘Smart Mapping Generator’

The release includes significant enhancements to the Smart Mapping File Generator, creating seamless compatibility between Technology Analyzer and Circuit Porting modules. The new system eliminates the need for manual parameter modifications, generating mapping files that work directly across both tools. Additionally, a template-based approach now supports custom device integration, allowing companies with proprietary device libraries to easily incorporate their components into the AMALIA workflow.

Strategic market impact

The AMALIA Platform 25.3 qualification for sub 10nm process technology, combined with its advanced feature set, directly addresses the critical needs of:

• Tier-1 fabless semiconductor companies: Enabling analog and mixed-signal IP development at advanced nodes for integration into next-generation SoCs, with automated solutions for complex layout migrations across multiple process technologies
• Integrated device manufacturers (IDMs): Providing comprehensive analysis tools and automation tools for in-house IC development spanning mature to advanced process nodes
• Leading-edge CMOS semiconductor foundries: Supporting sub 10nm process technologies, enabling enhanced design rule checking, migration support, and analog IP qualification
• Analog, mixed-signal, and RF IC design teams: Delivering specialized automation tools that understand the unique challenges of non-digital circuit design at both advanced and mature process nodesHigh-frequency modeling capabilities

High-frequency modeling capabilities

Building on previous releases, AMALIA Platform 25.3 continues to advance high-frequency modeling capabilities, supporting the demanding requirements of RF and high-speed analog applications. These enhancements enable accurate simulation and analysis of next-generation wireless, automotive radar, and high-performance computing designs.

Customer engagement and market validation

The platform's Smart Mapping Generator capabilities have been demonstrated to a major foundry partner, validating the approach for large-scale manufacturing environments. The auto-routing algorithm represents an entirely new capability class, developed through intensive collaboration with layout engineering teams to understand real-world migration challenges.

Availability and technical specifications

AMALIA Platform 25.3 will be available to customers from end of October 2025, with full technical documentation and support. The release includes comprehensive APIs for integration with existing design flows and extensive customization options for company-specific requirements.

About Thalia Design Automation

Thalia is a leading provider of analog, mixed-signal and RF IP design migration solutions. The company's AMALIA Platform harnesses advanced automation and AI/ML technology to streamline the migration process, enabling semiconductor companies to reduce time, cost and complexity while optimizing their ability to create innovative applications. Thalia serves customers worldwide across automotive, communications, consumer electronics and industrial markets. For more information, visit thalia-da.com.