Swiss Open-Source Processor Core Ready For IoT
Peter Clarke, EETimes
3/31/2016 10:48 AM EDT
Researchers at ETH Zurich (Swiss Federal Institute of Technology in Zurich) and the University of Bologna have developed PULPino, an open-source processor optimized for low power consumption and application in wearables and the Internet of Things (IoT).
Open-source and collaborative development is now standard practise in the software world – Linux being an example. While there have been hardware efforts, such as OpenRISC and Opencores, open-source hardware has gained the most traction at the board level. Examples include Arduino and Raspberry Pi, for which the PCB designs are publicly available. However, the chips on which those boards are based have remained proprietary.
Now a team led by ETH Professor Luca Benini, has put into the public domain the full design of one of their microprocessor systems, a derivative of the PULP (Parallel ultra low power) project.
The 32-bit PULPino is designed for battery-powered devices with extremely low energy consumption. The arithmetic instructions are also open source: the scientists made the processor compatible with an open-source instruction set – RISC-V – developed at the University of California in Berkeley.
To read the full article, click here
Related Semiconductor IP
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- 64-bit High Performance Out-of-Order Processor - Out-of-Order, 3/4/6-Wide Decode
- ARC-V RPX Series Functional Safety Processor IP
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- Neuromorphic Processor IP (Second Generation)
Related News
- Arm introduces new image signal processor to advance vision systems for IoT and embedded markets
- OpenHW Group Announces RISC-V-based CORE-V MCU Development Kit for IoT Built with Open-Source Hardware & Software
- XtremeEDA to enable IoT security deployment with Crypto Quantique's solution using Codasip's RISC-V processor
- Imperas leads the RISC-V verification ecosystem as the first to release an open-source SystemVerilog RISC-V processor functional coverage library
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack