Processor IP
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Configurable RISC-V processor IP core
- The NOEL3 is a configurable RISC-V processor IP core, described in VHDL.
- The architecture is designed to utilize a small area footprint and to maintain execution predictability.
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Nios® V Processor
- Nios® V processors are the next generation of soft processor IPs, designed to bring the power and flexibility of the open-source RISC-V Architecture to FPGA environments
- By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.
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Highly customizable processor IP supporting the Lua scripting language
- Native execution of the Lua scripting language
- Build-time configurable
- Run-time configurable
- Each processor core is heterogeneous
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8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA)
- 16/32-bit mixable instruction format for compacting code density
- Advanced low power branch predication to speed up control code
- Return Address Stack (RAS) to accelerate procedure returns
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ARC EM22FS safety processor
- Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
- Single solution support for safety level up to ASIL D; Supports both ASIL D lockstep operation or ASIL B single core operation
- Includes hardware safety features such as ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
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ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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ARC EM7D DSP Enhanced 32-bit processor core with caches, ARCv2DSP ISA, for low power embedded DSP ap
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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ARC EM5D Enhanced 32-bit processor core, ARCv2DSP ISA, for low power embedded DSP applications
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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ARC EM6 32-bit processor core with cache for embedded applications
- Very small size - 0.01mm2 (28 HPM)
- 1.81 DMIPS/MHz performance, 4.18 CoreMarks/MHz
- Up to 240 interrupts with 16 levels
- 512B - 2MB instruction closely coupled memory (ICCM)
