Perceptia Releases Design Kit for pPLL05 on GlobalFoundries 22FDX Platform

Sydney, Australia — July 31, 2025 — Perceptia Devices, a leader in high-performance clocking IP, today announced the availability of the design kit for its pPLL05 phase-locked loop IP on GlobalFoundries’ 22FDX® (22nm FD-SOI) technology node. The pPLL05 is a compact, ultra-low power, PLL optimised for integration into SoCs targeting low-power and battery operated applications. The release of the design kit enables SoC developers to efficiently incorporate the pPLL05 into their designs with full support for layout, simulation, and timing closure.

Key technical features of the pPLL05 include:

• Power consumption: less than 0.77mW at 1GHz
• Output frequency range: Up to 1 GHz, supporting integer and fractional-N operation
• Lock time: <300 reference clock cycles
• Compact footprint: Highly area-efficient implementation with minimal analog overhead.
  • 0.009 sq mm in 22FDX

The pPLL05 supports both integer-N and fractional-N synthesis, allowing for fine-grained frequency generation. Its all-digital control interface enables easy integration with standard digital flows and software-driven configuration.

“pPLL05 is engineered for power-constrained designs,” said Julian Jenkins, CTO at Perceptia. “By offering a fully validated design kit on GF’s 22FDX process, we’re enabling designers to confidently implement low-power timing architectures in FD-SOI designs that have very limited power budgets.”

GlobalFoundries’s 22FDX platform is tailored for low-power, high-density applications such as mobile, edge AI, RF connectivity, and embedded processing. The availability of pPLL05 in this process gives customers a differentiated clocking solution optimised for FD-SOI characteristics.

The pPLL05 design kit includes:

• Liberty (.lib) timing models
• Verilog and Verilog-A simulation models
• GDSII and LEF physical views
• CDL netlist
• Integration guidelines and layout constraints
• Comprehensive verification and characterisation data

The kit is available immediately to qualified licensees.

For licensing inquiries or to request a technical brief, contact sales@perceptia.com or visit www.perceptia.com.

About pPLL05

The pPLL05 is a compact, low-power phase-locked loop (PLL) IP core optimised for advanced process nodes.

Designed for use in a wide range of low-power performance applications including IoT and embedded systems.

About Perceptia Devices

Perceptia Devices is an IP and design services provider, based in Sydney, Australia. It is focused on high-speed and ultra-low-power mixed-signal semiconductor designs. Its specialization and innovation in all-digital PLLs, a distinction from its competitors, allows it to steadily build a portfolio of proprietary and patented architectures and circuits that bring value to demanding applications.

For more information or to request the pPLL05 datasheet, please contact:

📧 sales@perceptia.com

🌐 www.perceptia.com