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PLL IP

Welcome to the ultimate PLL IP hub! Explore our vast directory of PLL IP

Here, you will find a variety of PLL designs and architectures, each tailored to specific application needs, including fractional-N PLLs, integer-N PLLs, and Delay-Locked Loops (DLLs). These variants offer different advantages, such as reduced phase noise, higher frequency stability, and improved design flexibility. Additionally, some advanced PLL IPs incorporate features like spread spectrum clocking to minimize electromagnetic interference, making them suitable for use in sensitive electronic environments.

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Search (1,864)
Compare 1,864 PLL IP from 54 vendors (1 - 10)
  • 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
    • 055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz.
    • It consists of the ring VCO with frequency from 400 to 800MHz, a programmable feedback divider, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with internal loop filter, lock detector (LD) and programmable clock divider to obtain a required output frequency.
    • LO output signal is CMOS compatible.
    Block Diagram -- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
  • 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
    • Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
    • The Fractional-N PLL loop with 2GHz-4GHz VCO has high phase noise performance and ultra-fine frequency tuning step.
    • VCO Sub-band auto select (SAS) system allows to find automatically appropriate sub-band for VCO on locked PLL.
    Block Diagram -- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
  • 2.26GHz/2.46GHz Fractional-N LC Phase-Locked Loop with oscillator
    • 180XFAB_PLL_01 uses 2.25792GHz/2.4576GHz Phase locked loop frequency synthesizer for clock generation.
    • It consists of the following main sub-blocks: reference oscillator; main PLL loop: Fractional-N PLL and VCO blocks; secondary digital PLL loop: synchronization subsystem; dividers block: clock generation/delivery subsystem; voltage stabilizers.
    • High frequency synthesis is needed for both phase noise performance and ultra-fine frequency tuning step.
    Block Diagram -- 2.26GHz/2.46GHz Fractional-N LC Phase-Locked Loop with oscillator
  • 10MHz to 50MHz fractional-N PLL synthesizer
    • UMC 22nm ULP technology
    • 1.8V IO power supply
    • Double 0.8/1.0V Core power supply
    • Embedded low noise bias
    Block Diagram -- 10MHz to 50MHz fractional-N PLL synthesizer
  • ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
    • Clock generation based on a Digitally Controlled Oscillator (DCO)
    • 800 MHz < = DCO frequency < = 2400 MHz
    • Programmable clock frequency dividers for ADPLL loop and clock outputs
    • lock-in < 25 us
    Block Diagram -- ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
  • X-band (7.9 − 9.8GHz) High Performance Frac-N PLL
    • The NEXUS9X is a CMOS high performance PhaseLocked Loop (PLL) with integrated voltage controlled oscillator (VCO) and loop filter, designed to provide high flexibility in its use in order to adapt to a variety of applications.
    • It covers typically the frequency range [7.9 − 9.8]GHz over variations in process, voltage and temperature (PVT), which can be scaled up/- down by using frequency multipliers/dividers, depending on the application.
    Block Diagram -- X-band (7.9 − 9.8GHz) High Performance Frac-N PLL
  • All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
    • Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
    • Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
    • Small die area (< 0.05 sq mm), using a LC tank oscillator
    • Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
  • All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7
    • Fractional Multiplication with frequencies up to 8GHz
    • Extremely low jitter (sub 300fs RMS)
    • Small size  (< 0.05 sq mm)
    • Low Power (< 7mW)
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7
  • All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 12LPP/14LPP
    • Fractional Multiplication with frequencies up to 8GHz
    • Extremely low jitter (< 300fs RMS)
    • Small size  (< 0.05 sq mm)
    • Low Power (< 10mW)
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 12LPP/14LPP
  • All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP
    • Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
    • Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
    • Small die area (< 0.05 sq mm), using a LC tank oscillator
    • Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP
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