PLL IP
Welcome to the ultimate PLL IP hub! Explore our vast directory of PLL IP
Here, you will find a variety of PLL designs and architectures, each tailored to specific application needs, including fractional-N PLLs, integer-N PLLs, and Delay-Locked Loops (DLLs). These variants offer different advantages, such as reduced phase noise, higher frequency stability, and improved design flexibility. Additionally, some advanced PLL IPs incorporate features like spread spectrum clocking to minimize electromagnetic interference, making them suitable for use in sensitive electronic environments.
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Integer-N-PLL-based HF Frequency Synthesizer and Clock Generator with integrated Loop Filter and VCO
- This integer-N PLL synthesizes 3.3V-square-wave FVCO frequencies within the HF range from 2.424MHz up to 9.697MHz, by steps of 18.9393kHz, and provides one fourth of fVCO on two other outputs, FDEM and FDRV, which feature quadrature phase difference or no phase shift depending on the control bit PH_SEL.
- The PLL-locked state within ±0.08% of fVCO is signaled by a logic high level on the LOCK output.
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Multi-rate Audio 24-Bit DAC/PLL Core
- Operates from single 27/54MHz clock.
- Ideal for MPEG, AC-3, DVD systems
- Internally generates audio sample clocks
- Multi-sample rates: 32, 44.1, 48 KHz
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High Speed 16GHz PLL
- Type II ,3rd order low jitter PLL
- Auto calibration for process and temperature (USP)
- Programmable frequency using CSR registers
- 8/10/16GHz quadrature clocks
- Operating temperature -40 to 125
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40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
- Rail-to-Rail IQ ADC Input Capability
- 65dB IQ ADC SNR
- Programmable Full-Scale IQ DAC Output Current
- 65dB IQ DAC SNR
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40nm 1.1V 6.0GHz-9.4GHz Fractional-N RF PLL
- TSMC 40nm CMOS
- 6.0GHz-to-9.7GHz Buffered VCO PLL Output Coverage
- Scalable Power Consumption
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40nm 1.1V 2GHz-4.7GHz Fractional-N RF Quadrature PLL
- 2.0GHz-to-4.7GHz PLL Output Coverage
- Scalable Power Consumption
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40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
- 16MHz-to-2GHz PLL Output Coverage
- Scalable Power Consumption
- Three independent programmable PLL outputs
- Internal Calibration Engine and Convergence Algorithm
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4-Phase LC PLL on INTEL 16
- High performance design for meeting low jitter requirements including Ref Clock applications
- Implemented with Analog Bits’ proprietary LC architecture
- Low power consumption
- Integrated power supply regulation for low deterministic jitter
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All Digital Phase Locked Loop
- The iniADPLL is an all digital implementation of a phase locked loop. Plls are widely used in telecom applications for clock recovery, clock generation and clock supervision.
- Different phase dtectors (FIFO fill level, phase erros, and so on) may be used and can be adapted to perfectely fit the application.
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Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
- Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
- Entirely core voltage powered, needs no analog supply voltage
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Very fine precision: near 1 part per billion resolution
