IP Catalog > Analog IP > Clocking IP > PLL IP

PLL IP

Welcome to the ultimate PLL IP hub! Explore our vast directory of PLL IP

Here, you will find a variety of PLL designs and architectures, each tailored to specific application needs, including fractional-N PLLs, integer-N PLLs, and Delay-Locked Loops (DLLs). These variants offer different advantages, such as reduced phase noise, higher frequency stability, and improved design flexibility. Additionally, some advanced PLL IPs incorporate features like spread spectrum clocking to minimize electromagnetic interference, making them suitable for use in sensitive electronic environments.

All offers in PLL IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (1,863)
Compare 1,863 PLL IP from 55 vendors (1 - 10)
  • PLL
    • The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, risk, and cost in the development of Analog Front-End design
    • It can generate a stable high-speed clock from an ultra-wide input clock
    • With excellent supply noise immunity, the PLL is ideal for use in noisy mixed signal SoC environments
    Block Diagram -- PLL
  • Low Power 300-600 MHz programmable PLL
    • The WEAPLL400M22 is a low power integer PLL operating at a single 0.8 V power supply
    • This PLL has a wide programmable frequency range operation operating from 300 MHz up to 600 MHz
    • The VCO outputs are coming into 8 cascaded phases
    • The PLL needs a sourcing current of 2 uA in order to operate
    Block Diagram -- Low Power 300-600 MHz programmable PLL
  • General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
    • Output frequency range: 500MHz – 2GHz 
    • Loop bandwidth 60kHz – 180MHz 
    • 8 or 4 phase output clocks 
    • Output clock duty cycle 50 +5% 
    • Typically locks within 150 reference clock cycles 
    • Simple power-up sequence 
    • Lock indicator signal 
    Block Diagram -- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
  • Low Power PLL for TSMC 40nm ULP
    • Wide range M, P, and N integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Input frequency range 1.4MHz – 32MHz.
    • 18pS RMS cycle to cycle jitter.
    • Lock-detect function.
    • Optional bypass function.
    Block Diagram -- Low Power PLL for TSMC 40nm ULP
  • General Purpose PLL for TSMC 152nm
    • Wide range M integer divider. (See ot3122 for M, N, and P dividers)
    • 40MHz – 800MHz output frequency range.
    • Comparable frequency range 8MHz – 32MHz.
    • Optional prescaler.
    • 19pS RMS cycle to cycle jitter at 800MHz.
    • Lock-detect function.
    • Bypass function.
    • 20µS well defined fast startup behavior.
    Block Diagram -- General Purpose PLL for TSMC 152nm
  • 600MHz General Purpose PLL
    • Wide range M integer divider. (See ot3122 for M, N, and P dividers)
    • 250MHz – 600MHz output frequency range.
    • Comparable frequency range 8MHz – 50MHz.
    • 18pS RMS cycle to cycle jitter at 600MHz.
    • Lock-detect function.
    • Bypass function.
    • Well defined startup behavior.
    • -40°C to 140°C temperature operation.
    Block Diagram -- 600MHz General Purpose PLL
  • 1.2GHz General Purpose PLL for TSMC 0.18u Processes
    • Wide range N, M integer dividers.
    • 600MHz – 1.2GHz output frequency range.
    • Comparable frequency range 20MHz – 200MHz.
    • 18pS RMS cycle to cycle jitter at 1.2GHz.
    • Lock-detect function.
    • Bypass function.
    • Well defined startup behavior.
    • -40°C to 140°C temperature operation.
    Block Diagram -- 1.2GHz General Purpose PLL for TSMC 0.18u Processes
  • General Purpose PLL for VIS 150nm
    • Wide range N, M, P integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Comparable frequency range 8MHz – 50MHz.
    • 18pS RMS cycle to cycle jitter at 600MHz.
    • Lock-detect function.
    • Bypass function.
    Block Diagram -- General Purpose PLL for VIS 150nm
  • General Purpose PLL for TSMC 180nm
    • Wide range N, M, P integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Comparable frequency range 8MHz – 50MHz.
    • 18pS RMS cycle to cycle jitter at 600MHz.
    • Lock-detect function.
    • Bypass function.
    • Well defined startup behavior.
    Block Diagram -- General Purpose PLL for TSMC 180nm
  • PLL for TSMC 130nm LP
    • Wide range N, M, P integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Comparable frequency range 8MHz – 50MHz.
    • 18pS RMS cycle to cycle jitter at 400MHz.
    • Lock-detect function.
    • Bypass function.
    • Well defined startup behavior.
    • -40°C to 125°C temperature operation.
    • Small cell area: 0.022mm2 in 0.13µ CMOS.
    Block Diagram -- PLL for TSMC 130nm LP
×
Semiconductor IP