Andes 32-bit CPU IP Cores Implemented on GLOBALFOUNDRIES 22FDX Process Technology 2017-10-24 07:37:00 IP Cores & Design
BrainChip Ships First BrainChip Accelerator To a Major European Car Maker for Evaluation in ADAS and AV Systems 2017-10-24 04:57:00 SoC Architecture & Assembly
It's Here: A Common Industry Framework for Protecting a Trillion Connected Devices 2017-10-23 16:46:00 SoC Architecture & Assembly
SiFive Selects Synopsys Verification Continuum Platform for Advanced RISC-V Processor Designs 2017-10-23 15:09:00 EDA & Design Tools
90% Reduction in power consumption for RFID chips with Dolphin Integration's SESAME eLC standard cell library 2017-10-23 13:45:00 IP Cores & Design
OVH launches Acceleration-as-a-Service Leveraging the New Intel Programmable Acceleration Card and App Store from FPGA Acceleration Partner Accelize 2017-10-20 08:16:00 SoC Architecture & Assembly
ArterisIP Acquires iNoCs Software and Associated Intellectual Property Rights 2017-10-20 07:59:00 Strategic Partnerships
Rambus Validates Interoperability of DDR4 High-performance Memory IP Solution for Arm-based Datacenter Systems 2017-10-19 15:14:00 IP Cores & Design
Microsemi Launches Mi-V Ecosystem to Accelerate Adoption of RISC-V 2017-10-19 13:47:00 SoC Architecture & Assembly
CEVA and Cyberon Partner for Ultra-low Power Always-listening Voice Activation Solution 2017-10-19 13:31:00 SoC Architecture & Assembly
Inside Secure brings to market industry's only complete and fully-certified cloud-based mobile payment solution 2017-10-19 10:41:00 SoC Architecture & Assembly
M31 Technology and Corigine have launched the world's first USB-IF certified 28 nm Superspeed+ USB 3.1 Gen 2 IP Solution 2017-10-19 08:23:00 IP Cores & Design
Corigine Unveils First Certified SuperSpeed+ USB 3.1 Gen 2 IP With M31 28nm PHY 2017-10-18 17:00:00 IP Cores & Design