ROM IP
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293
IP
from 46 vendors
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10)
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Parameterizable ROM Built In Self Test Controller
- Fully static, synthesizable ROM BIST
- ROM Structure independent CRC Algorithms
- Master Slave, simultaneous multiple ROM Test
- Optional transparent Bypass Mode (hidden ROM test during scan test)
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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
- Ultra-low-leakage even in a generic process
- No leakage in memory plane
- Minimal leakage in memory periphery while achieving between 230 and 300 MHz in worst case in TSMC 90 nm LP !
- Key patent for high density with only one programming layer
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Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Ultra low dynamic power
- Decrease of packaging cost
- Smaller SoC area
- 45% less consuming than conventional metal or via ROM at nominal voltage
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Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Ultra low dynamic power
- Decrease of packaging cost
- Smaller SoC area
- 45% less consuming than conventional metal or via ROM at nominal voltage
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Metal programmable ROM compiler - Memory optimized for low power and high density - compiler range up to 1024 k
- Ultra low dynamic power
- Decrease of packaging cost
- Smaller SoC area
- 45% less consuming than conventional metal or via ROM
-
Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Ultra low dynamic power
- Decrease of packaging cost
- Smaller SoC area
- 45% less consuming than conventional metal or via ROM
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VeriSilicon GSMC 0.18um Synchronous Low Power Via1 ROM Compiler, Memory Array Range:128 to 2Mega Bits
- Low Power
- High Density
- Size Sensitive Self-time Delay for Fast Access and "Zero" Hold Time
- Automatic Power Down
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VeriSilicon GSMC 0.18um General Process, Low Power circuit design, Diffusion ROM
- Low Power
- High Density
- Size Sensitive Self-time Delay for Fast Access and "Zero" Hold Time
- Automatic Power Down
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VeriSilicon SMIC 0.13um Synchronous programmable Via1 ROM compiler,Memory Array Range:128 to 1Mega Bits
- High Density
- High Speed
- Size Sensitive Self-time Delay for Fast Access and "Zero" Hold Time
- Automatic Power Down
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SMIC 0.13um Synchronous Diffusion ROM
- High Density
- High Speed
- Size Sensitive Self-time Delay for Fast Access Time and "Zero" Hold Time
- Automatic Power Down