PAM4/NRZ SerDes IP
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15
IP
from 6 vendors
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10)
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112G-ULR PAM4 SerDes PHY
- Supports full-duplex 1.25Gbps to 112.5Gbps data rates
- Superior bit error rate (BER) performance across high-loss and reflective channels
- Compliant with IEEE 802.3ck and OIF standard electrical specifications
- Supports flexible SoC floorplan and IP placement and provides package substrate guideline/reference designs
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112G-ELR PAM4 SerDes PHY - TSMC 5nm
- TSMC 5nm FinFET CMOS Process
- Power-optimized for ELR and LR links
- Integrated BIST capable of producing and checking PRBS
- 56-112Gbps PAM4 or 1-56Gbps NRZ data rates
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56G-LR Pam4 SerDes PHY
- Supports Ethernet, FC, CPRI, and eCPRI protocols
- Compliant to IEEE 802.3ck and OIF standard electrical specifications
- Supports 56Gbps PAM4 and 28G, 10G, and sub-10Gbps NRZ data rates
- Unique firmware-controlled adaptive power design provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements
- Continuous calibration and adaption provide robust performance across process, voltage, and temperature
- Supports industrial temperature range -40°C – 125°C
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64G SerDes
- 4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
- Serialization/Deserialization interface width; 64/32/16bits; 64-bit parallel data path in PAM4 mode; 32-bit parallel data path in full-rate NRZ mode; 16-bit and 32-bit parallel data path widths in half-rate and quarter-rate modes
- Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines
- Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades
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112G SerDes USR & XSR
- 8 Channels per Macro, 2.5Gbps~112Gbps with TX/RX independent; NRZ Data Rate:2.5-56Gbps PAM4 Data Rates: 56-112Gbps
- Serialization/Deserialization interface width; PCS-User interface support 64bit in PIPE
- Two cascaded PLLs, one LC-tank based and the other ring-oscillator based
- Digitally-control-impedance termination resistors
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SerDes IP
- 10dB to 35dB bump-to-bump insertion loss
- Multi-rate support for 56Gbps to 112Gbps PAM4 and NRZ
- Integrated PLL
- Robust clock distribution architecture
- Advanced mixed signal analog equalization architecture
- Fully adaptive and programmable RX equalization
- Auto-negotiation
- Link Training
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64G High-speed SerDes
- The 64G SerDes PHY is a highly configurable PHY capable of supporting speeds up to 64Gbps within a single lane
- The PHY has been configured to support 64G PAM-4 and NRZ specifically, but the PHY itself can be configured to support a wide range of HS SerDes protocols through changes to the PCS layer and register settings
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1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
- High speed performance
- Low power architecture
- Sub-sampling clock multiplier
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PHY for PCIe 7.0 and CXL
- Architecture optimized for HPC, AI/ML, storage, and networking
- Ultra-long reach, low latency, and low power
- Advanced DSP delivers unmatched performance and reliability
- Comprehensive real-time diagnostic, monitor, and test features
- Bifurcation support for x1, x2, x4, x8, and x16 lanes
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112G Ethernet PHY in TSMC (N7, N5, N3P)
- Optimized for performance, power, and area
- Includes one, two, or four full-duplex PAM-4 transceivers (transmit and receive functions)
- Supports IEEE and OIF standards: IEEE 802.3ck, CEI-112G
- Includes auto-negotiation and link training capabilities – IEEE 802.3 clause 73