SerDes IP

Overview

Complete your custom Switch Fabric, AI, or HPC ASIC with Credo’s advanced SerDes IP. Our proven, innovative architecture is designed in TSMC’s 28nm, 16/12nm, N7/N6, N5/N4 and N3 processes. Whether you’re moving from 28G to 56G or 112G, we have SerDes IP for you. Credo designs SerDes IP that delivers industry-leading performance and power, but are manufactured in lower risk, lower cost mature processes.

Credo designs SerDes IP that optimally balances performance, power and manufacturing process costs and risks. Our unique, patented mixed signal architecture is the foundation for our high performance and low power SerDes technology. The architectural approach taken by Credo has enabled us to design in mature fabrication processes yet deliver leading-edge performance and power. Credo was the first to deliver 56G NRZ in 40nm, 56G PAM4 in 28nm and 112G PAM4 in 28nm.

By contrast, other industry solutions have moved to power-hungry designs in the most advanced silicon processing geometries for performance, yet struggle to meet the fundamental power requirements.

SerDes IP Availability

Our IP is designed for a variety of TSMC fabrication processes.

  TSMC 28nm TSMC 16nm/12nm TSMC 7nm
28G NRZ MR, LR MR, LR MR, LR
56G PAM4   VSR, MR, LR VSR, MR, LR
112G PAM4   XSR, VSR, MR, LR XSR, VSR, MR, LR

Key Features

  • Integrated PLL
  • Robust clock distribution architecture
  • Advanced mixed signal analog or DSP equalization architectures
  • Fully adaptive and programmable RX equalization
  • Auto-negotiation
  • Link Training
  • Excellent random jitter performance
  • Robust clock data recovery
  • Complete diagnostic suite
  • On-chip PRBS generation and checking
  • RX monitors
  • Loop back testing
  • JTAG/IEEE 1500
  • MCU per lane
  • Parameters
    • 28G NRZ MR, LR in 28nm, 16/12nm, N7/N6, N5/N4 and N3 processes
    • 56G PAM4 XSR, VSR, MR, LR in 16/12nm, N7/N6, N5/N4 and N3 processes
    • 112G PAM4 XSR, VSR, MR, LR in 16/12nm, N7/N6, N5/N4 and N3 processes
    • From a few dB to 35dB bump-to-bump insertion loss

Benefits

  • Benefits : Low Power
  • Excellent insertion loss handling for enterprise class backplane and optical applications.
  • High-performance supply noise immunity for SoC integration.
  • Build-in Analog calibration for handling process variation.

Block Diagram

SerDes IP Block Diagram

Applications

  • High speed wireline communication for HPC and AI SoCs

Deliverables

  • Verilog Model
  • LEF view
  • Timing Libraries
  • ATPG Model & Netlist
  • GDS
  • Spice Netlist
  • Usage Guide and Documentation Free Integration Review

Technical Specifications

Foundry, Node
TSMC 16/12nm
Maturity
Silicon Proven
Availability
Now
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Semiconductor IP