Accelerated confidence in simulation-based verification of RTL designs with Ethernet networking interfaces
Avery TSN Ethernet Verification IP provides a complete simulation-based func tional verification solution for core-level and SoC-level verification, including MAC and PHY models, protocol checking, and optional compliance test suite based on UNH-IOL test specifications. Additional integration with ARM® Fast Model integration enables running the TSN IP’s software stack in one fully integrated testbench.
With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests and work on more complex topologies, such as bifurcation. Avery compliance test suites offer effective core through chip-level tests, including those used in compliance workshops as well as extended tests developed by Avery to cover the specification features.
