The 64G SerDes PHY is a highly configurable PHY capable of supporting speeds up to 64Gbps within a single lane. The PHY has been configured to support 64G PAM-4 and NRZ specifically, but the PHY itself can be configured to support a wide range of HS SerDes protocols through changes to the PCS layer and register settings.
The hard-macro PHY is well-architected for IEEE and OIF protocols, with ESD structure and BIST function accommodated. This IP powers high-speed interconnectivity between chips, optics, and backplanes with the built-in low-jitter LC PLL to optimize the signal integrity. The Innosilicon 64G Long Reach SerDes solution meets the functionality, power, performance and area requirements of a variety of network applications.