IP Catalog > Interface IP > Interconnect IP > Serdes IP > 112G-ULR PAM4 SerDes PHY

112G-ULR PAM4 SerDes PHY

Overview

Accelerates AI and Hyperscale Data Center Applications

The 112G Ultra-Long-Reach (ULR) SerDes PHY delivers exceptional long-reach performance, optimized power and area that is ideal for next-generation hyperscale data center, artificial intelligence (AI), optical, and 5G wireless applications. The SerDes PHY IP supports PAM4 and NRZ signaling and data rates from 1G to 112G with industry-leading digital signal process (DSP) technology incorporating maximum likelihood sequence detector (MLSD) to support up to a 45dB channel. It enables reliable high-speed data transfer over backplane, direct-attached cable (DAC), chip-to-chip, and chip-to-module channels to support LR, MR, and VSR use cases.

Key Features

  • Supports full-duplex 1.25Gbps to 112.5Gbps data rates
  • Superior bit error rate (BER) performance across high-loss and reflective channels
  • Compliant with IEEE 802.3ck and OIF standard electrical specifications
  • Supports flexible SoC floorplan and IP placement and provides package substrate guideline/reference designs
  • Available in multiple advanced-process nodes, including 3nm, 4nm, 5nm, 6nm, and 7nm
  • Up to 800G Ethernet subsystem delivery with Cadence High-Speed Ethernet Controllers

Benefits

  • Production Quality: A large number of customer production tapeouts and SoC proof points
  • Robust Performance: ADC/DSP-based receiver architecture with MLSD and reflection cancellation techniques provide superior data recovery for lossy and reflective channels
  • Power and Area Efficiency: Optimized power efficiency with configurability and compact area
  • Standard Compliance: Compliant with IEEE802.3 and OIF 112G standards

Technical Specifications

Foundry, Node
TSMC 6nm, 7nm
Maturity
Silicon proven
TSMC
Silicon Proven: 6nm , 7nm
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