56G-LR Pam4 SerDes

Overview

56G LR SerDes PHY provides exceptional performance w/ best-in-class power & area, making it ideal for machine learning and 5G infrastructure apps

The Cadence 56Gbps Long Reach Quad-Lane SerDes IP for TSMC 7nm operates at a full-rate of 56Gbps using PAM-4 modulation, as well as 28/10Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The area- and power-optimized design is ideal for high port-density applications that require long-reach and medium-reach links.

Key Features

TSMC 7nm FinFET CMOS Process
56Gbps PAM-4 or 28/10Gbps NRZ data rates
Power-optimized for LR and MR links
Compact footprint for high-density designs
Fully autonomous startup and adaptation without requiring ASIC intervention
Integrated BIST capable of producing and checking PRBS
Best-in-class DSP supports long-reach lossy channels
Small area and low power is ideal for high port-density applications
Symmetric floorplan allows north-south and east-west SoC edge placement
Comprehensive on-chip diagnostic features make system testing/debugging quick and easy

Applications

Communications
Data Processing

Deliverables

GDS II macros with abstract in LEF
Verilog post-layout netlist
STA scripts for use at chip or standalone PHY levels
Liberty timing model
SDF for back-annotated timing verification

Technical Specifications

Foundry, Node

TSMC 7nm

Maturity

Silicon proven

TSMC

Silicon Proven: 7nm

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