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Analog IO IP

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Search (633)
Compare 633 IP from 45 vendors (1 - 10)
  • Analog I/O Library with a custom 12V ESD Solution IN GF 55nm
    • This I/O library is a silicon-proven, flip-chip-optimized analog and mixed-signal I/O Library for GlobalFoundries 55nm BCD technology.
    • It provides a comprehensive set of 1.8V, 3.3V, 5V, and 12V analog I/O and power pads, designed for robust ESD protection, flexible pad-ring construction, and reliable operation across industrial temperature ranges.
  • Specialed 20V Analog I/O in TSMC 55nm
    • A TSMC 55nm LP Specialized 20V Analog I/O in Standard Low Voltage CMOS
    • This silicon-proven TSMC 55nm LP 20V ESD cell is a high-voltage electrostatic discharge (ESD) protection solution specifically engineered forlow-power and high-performance applications.
    • This ESD cellis designed to safeguard high- voltage interfaces commonly found in analog, mixed-signal, RF, and power management ICs, where protection against electrostatic discharge events is critical for long-term reliability.
  • SMIC 65nm LL Standard analog IO
    • Standard analog IO;
    • Cell Size (Width * height) 50um * 123um;
    • Work voltage: 1.8V~3.3V analog input/output;
    • SMIC 65nm Mixed Signal and RF Salicide 1.2V/2.5V low leakage Process;
  • SMIC 65nm LL Standard analog IO
    • Standard analog IO;
    • Cell Size (Width * height) 55um * 80um;
    • Work voltage: 1.2V or 3.3V analog input/output;
    • SMIC 55nm Logic Salicide 1.2/2.5V Low Leakage Process and SMIC 55nm Mixed Signal and RF Salicide 1.2V/2.5V low leakage Process;
  • SMIC 65nm LL Standard analog IO
    • Standard analog IO;
    • Cell Size (Width * height) 50um * 123um;
    • Work voltage: 1.8V~3.3V analog input/output;
    • SMIC 65nm Logic Salicide 1.2/1.8/2.5/3.3V Low Leakage Process and SMIC 65nm Mixed Signal and RF Salicide 1.2V/2.5V low leakage Process;
  • SMIC 65nm LL Standard analog IO
    • Standard analog IO;
    • Cell Size (Width * height) 30um * 228um with DUP stagger bonding pads;
    • Work voltage: 1.2V or 1.8V analog input/output;
    • SMIC 0.065?m Logic Salicide 1.2V/1.8V low leakage Process;
  • SMIC 55nm LL Standard analog IO
    • Standard analog IO;
    • Cell Size (Width * height) 50um * 123um;
    • Work voltage: 1.2V or 3.3V analog input/output;
    • SMIC 55nm Logic Salicide 1.2/1.8/2.5/3.3V Low Leakage Process and SMIC 55nm Mixed Signal and RF Salicide 1.2V/2.5V low leakage Process;
  • SMIC 130nm G 300mA Analog IO and power cut cell
    • SMIC 0.13um Logic 1P8M Salicide 1.2V/3.3V Process
    • 300mA Analog IO and power cut cell.
  • Low-cap high-speed RF analog IO
    • Low-cap. high-speed RF analog IO, support >2GHz signal
    • Cell Size (Width * height) 60um * 126um with DUP in-line bonding pads
    • Work voltage: 1.1V/1.8V~3.3V power
    • SMIC 0.040um Logic Salicide 1.1V/2.5V low leakage Process
  • CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.
    • VeriSilicon CSMC 0.13μm 1.2V/3.3V DUP I/O Cell Library supports design with six, seven or eight layers of metal.
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