SMIC 55nm LL Standard analog IO
Key Features
- Standard analog IO;
- Cell Size (Width * height) 50um * 123um;
- Work voltage: 1.2V or 3.3V analog input/output;
- SMIC 55nm Logic Salicide 1.2/1.8/2.5/3.3V Low Leakage Process and SMIC 55nm Mixed Signal and RF Salicide 1.2V/2.5V low leakage Process;
- Suitable for 7, 8 and 9 layers application (single top metal);
- Suitable for 7, 8, 9 and 10 layers application (double top metal);
Technical Specifications
Foundry, Node
SMIC 55nm LL
Maturity
In Production
SMIC
In Production:
55nm
LL
Related IPs
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- SMIC 65nm LL 3.3V-2.5/1.2V Power Regulator
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- Single Wire Protocol (SWP) Master Analog Front End (AFE) compliant with the ETSI 102.613 standard
- Single Wire Protocol (SWP) Slave Analog Front End (AFE) compliant with the ETSI 102.613 standard