Agnisys IP
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10
IP
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10)
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Crossbars Interconnect
- APB
- AHB
- AXI
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Bus Convertors
- AXI
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Bus Bridges
- Supported Buses
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Bus Decoders
- Supported Buses
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TileLink Target
- TL-UL both 1.7 and 1.8 standard
- TL-UL: 'PutFullData', 'PutPartialData', 'Get', 'AccessAck', 'AccessAckData' and Error response
- All three messages above, with and without latency transaction
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Avalon Target
- Synchronous or asynchronous reset type
- Supports single clock data transfers
- Data Latency or wait stages
- Burst and non-burst transfers
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Wishbone Target
- Flopped and non-flopped
- Synchronous or asynchronous reset type
- Supports single clock data transfers
- Data Latency or wait stages
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AMBA APB Target
- Wait state
- Error reporting
- Transaction protection
- Sparse data transfer
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AMBA AHB Target
- Completely Configurable registers and memories
- Configurable bus width up to 64/128 bits
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AMBA AXI Target
- Completely Configurable registers and memories
- Configurable bus/address width
- Module has Asynchronous/Synchronous resets.