AMBA AHB Target
Overview
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
Key Features
- AHB3 Lite and Full featured
- Burst transfers supported
- Single clock-edge operation
- Non-tristate implementation
- Flopped and non-flopped outputs
- Synchronous or asynchronous reset type
- Low Data Latency
Deliverables
- Agnisys provides a tool - IDesignSpec to configure the IP.
Technical Specifications
Related IPs
- PCI to AMBA AHB Host Bridge
- PCI - AMBA AHB Device/Host Bridge
- SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- AMBA AHB 4 Channel DMA Controller
- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions