AMBA AXI Target
Overview
The "advanced extensible interface" (AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
Key Features
- Independent read and write channels
- Multiple outstanding addresses on single ID
- Support for unaligned data transfers
- Out-of-order transaction completion
- Burst transactions based on start address
- Flopped and non-flopped
- Synchronous or asynchronous reset type
- AXI4 lite, AXI4 full, and AXI5 lite
- Low Data Latency or wait stages
Deliverables
- Agnisys provides a tool - IDesignSpec to configure the IP
Technical Specifications
Maturity
Released
Availability
Now
Related IPs
- SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
- PCI Express to AMBA 4 AXI/3 AXI Bridge
- AMBA AXI STREAM Verification IP
- SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect