Wishbone Target
Overview
The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semiconductor IP cores. Its goal is to promote design reuse by addressing system-on-chip integration issues. This is accomplished by providing a standard interface for IP cores. This increases the system's mobility and stability, resulting in a shorter time-to-market for end users.
Key Features
- Flopped and non-flopped
- Synchronous or asynchronous reset type
- Supports single clock data transfers
- Data Latency or wait stages
Deliverables
- Agnisys provides a tool - IDesignSpec to configure the IP.
Technical Specifications
Maturity
Released
Availability
Now