TileLink Target
Overview
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. TileLink is intended for use in a System On-Chip (SoC) to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complicated devices, utilising a fast, scalable interconnect that provides both low latency and high-throughput transfers.
Key Features
- TL-UL both 1.7 and 1.8 standard
- TL-UL: 'PutFullData', 'PutPartialData', 'Get', 'AccessAck', 'AccessAckData' and Error response
- All three messages above, with and without latency transaction
Deliverables
- Agnisys provides a tool - IDesignSpec to configure the IP.
Technical Specifications
Maturity
Released
Availability
Now