Most wearables devices typically monitor a finite set of parameters which does not demand a lot of computing power and memory size. Thus any wearable design requires low power, lower RAM density and simplified inter face with optimal performances. These design requirements make PSRAM a natural choice for wearable applications. PSRAM has the advantages that there is no need of refresh control from external sources (unlike SDRAM) and active and standby currents are very low, therefore it has been adopted in many battery-operated mobile applications such as cellular phones and recently making its way into wearables and loT applications.
Mobiveil’s approach on this emerging scenario results in a PSRAM controller named “Octal SPI DDR PSRAM controller”.
This controller supports AP Memory’s Xccela open standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM. This controller enables smooth integration AP memory’s of Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’. This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling.
