IP Catalog > Foundries > TSMC > Memory & Libraries IP > Embedded Memories IP > RAM IP

RAM IP for TSMC

Welcome to the ultimate RAM IP for TSMC hub! Explore our vast directory of RAM IP for TSMC
All offers in RAM IP for TSMC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (85)
Compare 85 RAM IP for TSMC from 8 vendors (1 - 10)
  • Ultra Low Power Embedded SRAM - TSMC 22ULL
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
    • Configurable mux factor sets column length and overall aspect ratio
    • Bit Line Voltage control eliminates potential low operating voltages issues
    Block Diagram -- Ultra Low Power Embedded SRAM - TSMC 22ULL
  • Ultra Low Voltage Embedded SRAM - TSMC 22ULL
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
    • ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
    • Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
    Block Diagram -- Ultra Low Voltage Embedded SRAM - TSMC 22ULL
  • Ultra Low Power Embedded SRAM - TSMC 28HPC+
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
    • Configurable mux factor sets column length and overall aspect ratio
    • Bit Line Voltage control eliminates potential low operating voltages issues
    Block Diagram -- Ultra Low Power Embedded SRAM - TSMC 28HPC+
  • Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
    • ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
    • Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
    Block Diagram -- Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
  • Ultra Low Voltage Embedded SRAM - TSMC 40ULP
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
    • ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
    • Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
    Block Diagram -- Ultra Low Voltage Embedded SRAM - TSMC 40ULP
  • High-Density eMRAM Compiler TSMC 22ULL
    • eMRAM compiler enabling low-power designs requiring high memory capacity
  • TSMC CLN5FF High Density Single Port SRAM Compiler
    • The High Density Single Port SRAM operates within voltage range from 0.675 V to 0.825 V and junction temperature range from -40 °C to 125 °C. The available supported macro size is configurable from 512 bits to 576K bits. The Compiler is divided into 1 groups according to their column selection numbers (Mux=8).
    • ? Pins and metal layers
    • – 1P3M (1X_h_1Xb_v): 3 metal layers used and top metal is MXb.
    • – Power mesh supported with M3 pins
  • TSMC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
    • High Density
    • High Speed
    • Size Sensitive Self-Time Delay for Fast Access
    • Automatic Power Down
  • Low power, high speed, and high density configurable Double Density SRAM
    • Based on patent-pending 1T cell design
    • Implemented with unmodified standard CMOS logic process
    • Best-in-class active power, leakage current, density, and speed
    • Supports large instances (e.g. 32Mbit)
×
Semiconductor IP