Single Port SRAM compiler - Memory optimized for ultra high density and low power - compiler range up to 576 k
Overview
Single Port SRAM compiler - TSMC 40 nm LP - Non volatile Memory optimized for ultra high density and low power - compiler range up to 576 k
Key Features
- Configuration
- SVT transistors for memory periphery
- HD HVT Pushed rule bit cell from foundry
- Smart periphery design
- To reach the highest density
- Features for low power
- Partitioned array to reach ultra low power consumption
- Stand by mode
- Data retention mode at nominal voltage (1.1 V) and low voltage (0.9 V)
- Smooth support of different working modes
- VENUS-eS option of the generator endowed with embedded switches
- Flexible architecture
- Innovative banking approach to propose several performance trade-offs for any memory size
- Multiple form factors
- Variable write-mask capability
- Safety of integration
- Data range flexibility allows easy addition of bits for ECC purposes
- Address range flexibility allows easy addition of single rows
- Robust power grid sizing to prevent IR drop and electromigration effects
- Metal 4 partially available for routing
Technical Specifications
Maturity
Pre-silicon
TSMC
Pre-Silicon:
40nm
LP
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- Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k