High-Density eMRAM Compiler TSMC 22ULL

The Synopsys Foundation IP optimized for the TSMC’s 22nm Ultra Low Leakage (ULL) process provides designers an extensive offering of high-speed,
high-density, ultra-high density, and eMRAM compilers, logic libraries, and GPIO solutions that are extensively proven in silicon, reducing project risk, and speeding time-to-market.

Built-in power management advanced features Synopsys Foundation IP on TSMC 22ULL process enables SoC designers to explore power, performance and area (PPA) tradeoffs to generate optimal memory configurations. It includes duet packages of embedded memories and logic libraries with standard cells, SRAMs, register files, ROMs, High-Performance Core (HPC) Design Kits, and Power Optimization Kits (POKs)—all the foundation IP elements needed to design ultra- low power SoCs (Figure 1). The integrated STAR Memory System (SMS) enables the test and repair of embedded memories, delivering high test quality and
yield while lowering overall chip area. Synopsys Foundation IP for TSMC 22ULL process includes 1.8V/3.3V GPIO with 1.8V/3.3V Tolerant and Failsafe operation and the complete hardened 1.8V/3.3V SD/eMMC PHY solution compliant with eMMC 5.1 and SD v6.0.

Synopsys Foundation IP for TSMC 22ULL solution enables designers of consumer, mobile, IoT, AIoT and automotive applications that require high speed, low leakage, and low power to achieve the best combination of PPA for their SoC designs.