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IP for GLOBALFOUNDRIES

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Compare 132 IP for GLOBALFOUNDRIES from 16 vendors (1 - 10)
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  • 12nm
  • All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 12LPP/14LPP
    • Fractional Multiplication with frequencies up to 8GHz
    • Extremely low jitter (< 300fs RMS)
    • Small size  (< 0.05 sq mm)
    • Low Power (< 10mW)
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 12LPP/14LPP
  • All Digital Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP
    • Fractional multiplication with frequency up to 4GHz
    • Low jitter (< 10ps RMS)
    • Small size  (< 0.01 sq mm)
    • Low Power (< 5mW)
    • Support for multi-PLL systems
    Block Diagram -- All Digital Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP
  • General Purpose All Digital Fractional-N PLL in GlobalFoundries 12LPP/14LPP
    • Low jitter (< 18ps RMS)
    • Small size  (< 0.01 sq mm)
    • Low Power (< 3.5mW)
    • Support for multi-PLL systems
    Block Diagram -- General Purpose All Digital Fractional-N PLL in GlobalFoundries 12LPP/14LPP
  • Low Power All Digital Fractional-N PLL in GlobalFoundries 12LPP/14LPP
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    • Reference clock from 5MHz to 200MHz
    Block Diagram -- Low Power All Digital Fractional-N PLL in GlobalFoundries 12LPP/14LPP
  • Low Power All Digital Fractional-N PLL in GlobalFoundries 22FDX
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.01 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 200 times the input reference, up to 1.0GHz
    Block Diagram -- Low Power All Digital Fractional-N PLL in GlobalFoundries 22FDX
  • Ultra-short reach SerDes with 500 Gbit/s throughput
    • 2x to 4x throughput at 50% or less energy consumption as compared to conventional SerDes over the same number of pins/wires
    • High pin-efficiency and low power
    • 208.3 Gbit/s full-duplex bandwidth per mm of die edge (500 Gbit/s for 2.4 mm of die edge)
    Block Diagram -- Ultra-short reach SerDes with 500 Gbit/s throughput
  • 1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm
    • A radiation-hardened GlobalFoundries 12nm LP/LP+ Flip-Chip IO library with both 1.8V and 3.3V GPIO, fail-safe GPI, analog cell, and associated ESD. Also features an LDO optimized for use with 3.3V GPIO.
    • This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function.
    Block Diagram -- 1.8V and 3.3V Radiation-Hardened GPIO with Optimized LDO in GF 12nm
  • GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
    • The 2.5Gbps LVDS transceiver in GlobalFoundries LP/LP+ is designed for high-speed, low-power data transmission in radiation-intensive environments.
    • Engineered with a Rad-Hard by Design approach, the Rad-Hard cells have been proton tested to 64 MeV with a flux exceeding 1.3E+09, and is latch-up proven to 200mA across -40C to 125C, ensuring robust immunity against TID, SEE, and SEL effects.
    Block Diagram -- GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
  • GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
    • This SLVS I/O Library delivers a robust, high-performance solution for high-speed differential signaling in GlobalFoundries 12nm process technology.
    • Designed for optimal signal integrity, this 0.8V SLVS transceiver features fast rise and fall times, low propagation delay, and built-in pre-emphasis to enhance signal quality over longer traces.
    • With support for data rates up to 3Gbps, it enables reliable, low-power communication while maintaining excellent noise immunity.
    Block Diagram -- GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
  • eFPGA on GlobalFoundries GF12LP
    • All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee. Complete machine readable descriptions of standard architectures can be found in the Logiklib open source repository.
    • The Z1000 standard eFPGA architecture has been ported to the GlobalFoundries GF12LP process.
    Block Diagram -- eFPGA on GlobalFoundries GF12LP
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