Analog IP for GLOBALFOUNDRIES

Compare 71 Analog IP for GLOBALFOUNDRIES from 7 vendors (1 - 10)

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12nm

FracN/SSCG PLL on GLOBALFOUNDRIES 12LP+
- Electrically Programmable PLL with Fractional-N divider and Spread Spectrum Clock Generation
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Ability to generate precise system clocks synchronized to track remote sources
- Very fine precision: near 1 part per billion resolution
Sleep Management Subsystem
- Power-On-Reset
- Programmable relaxation oscillator
- Low Power Comparator
Power Management Subsystem
- The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
- Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
- The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.
Sensor Interface Subsystem
- The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs.
- Featuring multiple Analog-to-Digital Converters (agileADC), Digital-to-Analog Converters (agileDAC), low-power programmable analog comparators (agileCMP_LP), and an associated reference generator (agileREF).
- The agileSensorIF Subsystem enables easy interaction with the analog world.
Low Drop-Out Linear Regulator
- The agileLDO is a linear Low Drop-Out voltage regulator (LDO) providing precision and programmable voltage regulation.
- The regulator architecture provides a high dynamic performance making it suitable for demanding digital applications.
- Whilst the low noise and high PSRR lends itself to powering noise-sensitive analog circuits.
8/10-bit Digital-to-Analog Converter
- The agileDAC GP is a digital-to-analog converter that uses a traditional capacitive DAC architecture.
- The agileDAC uses its own internal reference voltage.
- The architecture can achieve up to 10-bit resolution at sample rates up to 16 Msps.
12-bit Analog-to-Digital Converter
- The agileADC 12 Analog-to-Digital Converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 12-bit resolution at sample rates up to 64 MSPS. It includes a 16-channel input multiplexor that can be configured to be buffered or unbuffered, and support differential or single-ended inputs.
Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution