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BCH IP

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Compare 29 BCH IP from 10 vendors (1 - 10)
  • DVB-S2-LDPC-BCH IP
    • Irregular parity check matrix
    • Layered Decoding
    • Minimum sum algorithm
    • Soft decision decoding
    Block Diagram -- DVB-S2-LDPC-BCH IP
  • Block Diagram -- BCH Encoder and Decoder IP Core
  • BCH Decoder IP
    • BCH decoder compliant with the DVB-T2/S2 standard.
    • Available for Altera/Xilinx FPGA or ASIC implementation.
    • High speed design.
    • BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
    Block Diagram -- BCH Decoder IP
  • DVB-S2X Wideband BCH and LDPC Decoder
    • Compliant with DVB-S2 and DVB-S2X
    • Support for decoding of BBFRAMEs
    • Support for ACM, CCM, and VCM
    Block Diagram -- DVB-S2X Wideband BCH and LDPC Decoder
  • BCH Decoder
    • BCH decoder compliant with the DVB-T2/S2 standard.
    • Available for Altera/Xilinx FPGA or ASIC implementation.
    • High speed design.
    • BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
    • Area and power optimized implementation.
    Block Diagram -- BCH Decoder
  • 5G Polar Intel® FPGA IP
    • The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration into your wireless design
    • Polar codes represent an emerging class of error correction supporting the high throughput requirements for 5G new radio (NR).
    Block Diagram -- 5G Polar Intel® FPGA IP
  • Polar Encoder / Decoder for 3GPP 5G NR
    • The patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed.
    • The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance.
    Block Diagram -- Polar Encoder / Decoder for 3GPP 5G NR
  • 512B/ECC16 Nand Flash BCH Encoder/Decoder
    • 2-16 bit error correction
    • 2-900 data bytes per block
    • Low-latency, synchronous design
    • Pipelined correction operation supports 3 concurrent corrections
  • DVB-C2 Receiver (including LDPC and BCH decoder)
    • Compliant with ETSI 302 769 (DVB-C2).
    • Support for short blocks (16200 bits) and long blocks (64800 Bits).
    • Support for all modulation schemes (16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM).
    • Support for all interleaving schemes of all modulation schemes.
  • DVB-S2 BCH and LDPC Encoder and Decoder
    • Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2).
    • Support for short blocks (16200 bits) and long blocks (64800 bits).
    • Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, 32-APSK).
    • Support for all interleaving schemes of all modulation schemes.
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