WCDMA Release 9 compliant Viterbi Decoder

Overview

Key Features

• WCDMA Release 9 Compliant
• Implements Viterbi decoder to address the convolution encoded bit stream as defined in Section 4.2.3.1 of the specification 3GPP TS 25.212 V 9.5.0 Release 9
• Supports all block sizes i.e., K=40 – 504.
• Constraint length of 9
• Configurable Code rate of 1/2 and 1/3 with rate matching for other code rates supported
• Easy interface definition
• Easy support for rate matching and bit collection
• Customization to AXI or Avalon bus interface supported.
• Bit accurate simulation models available for RTL test vector generation.

Benefits

• Easily portable across various FPGA families from different vendors
• Customization support available
• Optimized for performance and area

Block Diagram

Applications

• W CDMA Forward error correction block

Deliverables

• Licensable in Netlist or Verilog or VHDL source format
• Target technology – Xilinx, Altera, Lattice devices
• Test bench
• C, VHDL, Verilog simulation models available
• Detailed technical documentation

Technical Specifications