Clock Generator PLL IP

Compare 429 Clock Generator PLL IP from 17 vendors (1 - 10)

10 to 40 MHz crystal oscillator
- Supply voltage 3.3V
- Output frequency 10-40MHz
- GF 180nm MCU CMOS technology
Phased-locked loop 120 to 950 MHz
- iHP SGB25V
- Wide frequency range (120…950 MHz)
- Operating frequency selection using external components
- Built-in switched capacitor sections for VCO frequency adjustment
Phase-locked loop system 2.8 to 3.3 GHz
- SMIC CMOS 0.18 um
- Wide frequency range (2.8…3.3 GHz)
- Built-in switched capacitors sections for VCO frequency adjustment
- Low noise figure
General-purpose & Specialized Ring PLLs + RTL-based Solutions
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
1.68 to 1.917 GHz Phase-Locked Loop
- AMS SiGe BiCMOS 0.35um
- Reference frequency from 10MHz to 125MHz
- LO1 frequency range from 1.692GHz to 1.973GHz
- LO2 frequency range from 175MHz to 225MHz
Frequency synthesizer 20 to 300 MHz
- iHP SGB25V
- Wide frequency range (120…950 MHz)
- Operating frequency selection using external components
- Built-in switched capacitor sections for VCO frequency adjustment
Charge pump
- AMS BiCMOS 0.35 um
- Adjustable output current
- Phase-frequency detector (PFD) reset circuit
- Differential input signal
Phase-frequency detector in ECL logic
- AMS BiCMOS 0.35 um
- Differential structure
- Ability to work with VCOs with both positive and negative frequency dependence of the control voltage
- Input frequencies up to 100MHz
20 to 300 MHz frequency synthesizer
- SilTerra CMOS 0.18 um
- 1V CMOS input logic signal
- Output current digital 3-bit adjustment (from 0.75 mA to 6.5 mA)
- 1.6 Gbps (DDR MODE) switching rates for transmitter
10MHz to 50MHz fractional-N PLL synthesizer
- UMC 22nm ULP technology
- 1.8V IO power supply
- Double 0.8/1.0V Core power supply
- Embedded low noise bias
$Block Diagram -- 10MHz to 50MHz fractional-N PLL synthesizer$