40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
Overview
The TRV301TSM40LP IP is a 1.1V low-power low-silicon-area 16MHz-to-2GHz Fractional-N Clock PLL implemented in TSMC Low-Power 40nm CMOS process technology. Its low loop filter bandwidth and low-frequency reference clock makes it especially suitable for use in clock synthesis for DAC, ADC and digital subsystems within wireless communication and broadcast integrated circuit chipsets (LTE, WiFi, WiMAX, DAB, DAB+, FM, HDFM, DRM, etc).
Key Features
- 16MHz-to-2GHz PLL Output Coverage
- Scalable Power Consumption
- Three independent programmable PLL outputs
- Internal Calibration Engine and Convergence Algorithm
- Fully-integrated 165kHz loop filter
- 13MHz to 52MHz Crystal Oscillator Reference Support
Benefits
- Low-power and low-area fully-featured 16MHz-to-2GHz Clock PLL with programmable outputs and integrated calibration engine and tuning voltage convergence logic.
Block Diagram
Applications
- PLL is suitable for embedding in ASIC and SoC subsystems for:
- LTE, WiFi, WiMAX, DAB, DAB+, FM, HDFM, DRM and many more
Deliverables
- Behavioural Models
- Timing Models
- GDSII Layout Database
- Netlist for LVS verification
- Usage and Integration Guidelines
- Databook
Technical Specifications
Foundry, Node
TSMC 40nm CMOS
Maturity
Contact Tetrivis
Availability
GDSII available in January 2015
Related IPs
- 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
- Ultra-Low Power Fractional-N digital PLL for IoT Applications in 40nm CMOS
- 40nm 1.1V 2GHz-4.7GHz Fractional-N RF Quadrature PLL
- 40nm 1.1V 6.0GHz-9.4GHz Fractional-N RF PLL
- Power on Reset IP, Vrr: 1.2V, Vfr: 1.1V, UMC 0.18um LL process
- Audio PLL - Fractional-N ±0.05 ppm accuracy