PLL is an automatic control system adjusting controlled oscillator frequency to be equal to reference oscillator frequency multiplied by a given integer. Frequency adjustment is carried out by using negative feedback. A phase detector compares a controlled oscillator output with a reference signal. The result is a charge pump current output that supplies external feedback filter and converted to a voltage for controlled oscillator adjustment.
Clock divider is used to generate signals with specified frequency. Delta-sigma modulator makes it possible to operate with reference oscillator of different frequency.
The block is fabricated on SMIC CMOS 0.18 um technology.
Phase-locked loop system 2.8 to 3.3 GHz
Overview
Key Features
- SMIC CMOS 0.18 um
- Wide frequency range (2.8…3.3 GHz)
- Built-in switched capacitors sections for VCO frequency adjustment
- Low noise figure
- High lock detector accuracy
- Charge pump low output current disbalance
- Low current consumption
- Low power consumption
- No external components required
- Portable to other technologies (upon request)
Block Diagram
Applications
- Portable transmitters
- Portable transceiver
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
SMIC CMOS 0.18 um
Maturity
silicon proven
Availability
Now
SMIC
Silicon Proven:
180nm
G