10MHz to 50MHz fractional-N PLL synthesizer

Overview

APLL Fractional-N phase locked loop frequency synthesizer is intended for SoC clock generation and embeds a reference 10MHz – 50MHz XTAL oscillator, which is also able to work as an input signal buffer in the same frequency range. The internal 2.5GHz high frequency VCO provides both excellent phase noise performance and ultra-fine frequency tuning step. The PLL is supplied from 1.8V input voltage down converted by embedded LDOs with low noise and high PSRR. The embedded Bias block provides a low noise and high PSRR voltage and current references to PMU, PLL core and XTAL blocks, as well as it outputs a voltage reference 1.0V for external purposes with up to 10uA load.

Key Features

  • UMC 22nm ULP technology
  • 1.8V IO power supply
  • Double 0.8/1.0V Core power supply
  • Embedded low noise bias
  • Reference frequency 10MHz÷50MHz
  • 2.25GHz/2.46GHz VCO
  • Reference frequency accuracy: ±20ppm
  • Supported audio clock sample frequencies: 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz
  • Audio clock frequency generation (MCLK):
    • - 11.2896MHz, 12.288MHz, 22.5792MHz, 24.576MHz, 45.1584MHz, 49.152MHz
  • Output frequency fine tuning range: ±1000ppm
  • Output frequency fine tuning step: 1ppb
  • RMS jitter: 2ps@20Hz–20kHz
  • APLL current consumption:
    • - 3.8mA in active PLL mode
    • - 0.5mA in standby mode (XTAL and PMU are working)
  • Embedded high-performance PMU:
  • Adjustable output voltage
  • 10mA load current
  • 0.8V power supply for external blocks
  • LDO PSRR: -65dB @1kHz
  • LDO noise: 40 nV/?Hz @10kHz
  • APLL area with pads: 0.95mm2 actual silicon value

Applications

  • Audio applications
  • DAC and ADC Clocks
  • I2S and I8S clocks

Deliverables

  • Schematic or NetList
  • Abstract view (.lef and .lib files)
  • Layout (optional)
  • Behavioral model (for functional verification)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Technical Specifications

Foundry, Node
UMC 22nm ULP technology
Maturity
silicon proven
Availability
Now
UMC
Silicon Proven: 22nm
×
Semiconductor IP