Xilinx Skips 10nm
At TSMC's OIP Symposium recently, Xilinx announced that they would not be building products at the 10nm node. I say "announced" since I was hearing it for the first time, but maybe I just missed it before. Xilinx would go straight from the 16FF+ arrays that they have announced but not started shipping, and to the 7FF process that TSMC currently have scheduled for risk production in Q1 of 2017. TSMC already have yielding SRAM in 7nm and stated that everything is currently on-track.
To read the full article, click here
Related Semiconductor IP
- Hardware Security Module (HSM) for AMD Xilinx Versal ACAP device
- Hardware Security Module (HSM) for Xilinx Zynq UltraScale+ MPSoC platform
- ARC4 Core for Xilinx FPG
- Xilinx Virtual Cable
- Xilinx HMC Controller
Related Blogs
- Altera Back to TSMC at 10nm? Xilinx Staying There
- PLD Overview: Xilinx and Altera
- Xilinx ARMs FPGAs, Altera to MIPSify Them
- Intel Eyeing Xilinx?
Latest Blogs
- Why What Where DIFI and the new version 1.3
- Accelerating PCIe Gen6 L0p Verification for AI & HPC Designs using Synopsys VIP
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Efficiency Defines The Future Of Data Movement
- Why Standard-Cell Architecture Matters for Adaptable ASIC Designs