Xilinx ARMs FPGAs, Altera to MIPSify Them
October 29, 2009
Good news for the FPGA masses who want access to the ARM ecosystem of operating systems, tools, IP, and applications — last week Xilinx and ARM announced their collaboration to enable ARM processors and interconnect on Xilinx FPGAs. This new dimension of the Xilinx Targeted Design Platform is a dramatic shift by Xilinx, away from their traditional IBM Power PC Architecture.
Related Semiconductor IP
- I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
- I2C Controller IP – Master, Parameterized FIFO, Avalon Bus
- I2C/SMBus Controller IP – Master / Slave, Parameterized FIFO, AXI/AHB/APB/Avalon Buses, SMBus Protocol
- I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
- I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
Related Blogs
- Altera and Xilinx Eyeing 28nm FPGA Dominance
- Xilinx Beats Altera to the First FinFET FPGA!
- PLD Overview: Xilinx and Altera
- Altera at 28nm: rethinking the FPGA