The Age of AI Demands Faster Chip Development: Only Arm and Cadence Deliver
Strategic collaboration accelerates Custom Silicon for evolving AI workloads
As AI continues its rapid evolution, optimized silicon is crucial to unlock next-generation applications. Arm serves as a foundation for this innovation with its CPU, GPU and related technologies and pioneering solutions like the Arm Neoverse Compute Subsystems (CSS), introduced earlier this year.
CSS are validated and performance-optimized subsystems – building blocks seamlessly integrated into systems-on-chip (SoCs) – designed to mitigate risk, reduce non-recurring engineering (NRE) costs, and expedite the time to market. Neoverse CSS gives partners the flexibility needed to take these building blocks, tailor them for cutting-edge process nodes, and enable access to custom acceleration for new AI applications. Considering the increased complexity of CSS and the level of expertise needed to assemble a competitive CSS, software is a critical component of each delivery, from drivers all the way to the application layer, with partner-specific workloads used to optimize performance and power.
This process involves taking Arm Neoverse platform IP and refining it for enhanced performance, power efficiency, and area optimization, using a state-of-the-art foundry processes. This initiative is an integral part of Arm Total Design, an ecosystem program designed to smooth and speed delivery of customized SoCs, a critical aspect in the era of AI.
Related Semiconductor IP
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
- High Speed Ether 2/4/8-Lane 200G/400G/800G PCS
Related Blogs
- Arm Ethos-U85: Addressing the High Performance Demands of IoT in the Age of AI
- Navigating the Future of EDA: The Transformative Impact of AI and ML
- DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers
- Cadence and Arm Are Building the Future of Infrastructure
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?