Technical Comparison: MIPI MPHY 3.1 vs MPHY 3.0
Recently MIPI Alliance has announced the M-PHY version 3.1 specification. We are very excited about the new version and have already launched world's first MIPI MPHY 3.1 Verification Solution. M-PHY 3.1 introduces some new configuration attributes, some timing calculation modification and some other changes that we will describe below. The new specification does not introduce any new transfer speed/gear configurations.
In terms of benefits, when compared to MPHY 3.0, there is an improvement in power optimization, false line state detection (LINE_RESET) and general cleanup of timer timeouts etc. In this blog, we are going to summarize the main technical differences between M-PHY 3.1 and M-PHY 3.0 specifications. Hopefully, these will help you hit the ground running!
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- Technical Comparison - MPHY 3.0 vs MPHY 2.0
- USB 3.1 vs USB 3.0: Technical Comparison
- USB 3.1 vs USB 3.0: Technical Comparison
- Technical Comparison: MIPI UniPro 1.6 vs MIPI UniPro 1.41
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?