Unraveling the Newly Introduced Segmentation in PCIe 6.0
The PCIe protocol evolved to its sixth generation in 2021, doubling its transfer rate to 64 GT/s compared to the previous generation and bringing new features and optimizations to move dependency from software to hardware.
The PCIe hierarchy can be treated as a tree that is rooted in the root port. Each hierarchy can have up to 256 buses. Each bus can host 32 devices, and each device can host eight functions. The tuple of bus/device/function numbers (or just bus/function numbers, in alternative routing ID case) are unique within a hierarchy. In some contexts, the hierarchy is also called a segment.
Does Segmentation Exist Before PCIe 6.0?
To read the full article, click here
Related Semiconductor IP
- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 6.0 / CXL 3.0 PHY & Controller
- PCIe 6.0 Retimer Controller with CXL Support
- PHY for PCIe 6.0 and CXL
Related Blogs
- PCIE 6.0 vs 5.0 - All you need to know
- Big Innovations Double the Data Rate to 64 GT/s with PCIe 6.0
- Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0
- Unraveling PCIe 6.0 FLIT Mode Challenges
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power