Unraveling the Newly Introduced Segmentation in PCIe 6.0
June 27, 2024
The PCIe protocol evolved to its sixth generation in 2021, doubling its transfer rate to 64 GT/s compared to the previous generation and bringing new features and optimizations to move dependency from software to hardware.
The PCIe hierarchy can be treated as a tree that is rooted in the root port. Each hierarchy can have up to 256 buses. Each bus can host 32 devices, and each device can host eight functions. The tuple of bus/device/function numbers (or just bus/function numbers, in alternative routing ID case) are unique within a hierarchy. In some contexts, the hierarchy is also called a segment.
Does Segmentation Exist Before PCIe 6.0?
To read the full article, click here
Related Semiconductor IP
- PCIe 6.0 Retimer Controller with CXL Support
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
- PCIe 6.0 (Gen6) Premium Controller
- Adds security Interfaces, features to PCIe 6.0 Premium controllers (Gen6)
Related Blogs
- PCIE 6.0 vs 5.0 - All you need to know
- Big Innovations Double the Data Rate to 64 GT/s with PCIe 6.0
- Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0
- Unraveling PCIe 6.0 FLIT Mode Challenges
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms