What Does SystemC Mean for Design and Verification?
August 23, 2011
My colleague Jack Erickson recently published in the Cadence System Design and Verification Community a blog post entitled "IP Cannot Be an Efficient Abstraction Level without SystemC!" When I saw the title, my immediate reaction was to write a complementary post called "SystemC Cannot Be an Efficient Abstraction Level without IP!" This caused me to think some about the industry momentum toward using SystemC rather than traditional RTL as a design language. I chose a more general title because there are three key points I want to hit.
To read the full article, click here
Related Semiconductor IP
- ISO/IEC 7816 Verification IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
Related Blogs
- Randomization considerations for PCIe Integrity and Data Encryption Verification Challenges
- Smarter SoC Design for Agile Teams and Tight Deadlines
- Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple
- 4 Ways that Digital Techniques Can Speed Up Memory Design and Verification
Latest Blogs
- A Comparison on Different AMBA 5 CHI Verification IPs
- Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
- Accelerating Development Cycles and Scalable, High-Performance On-Device AI with New Arm Lumex CSS Platform
- Desktop-Quality Ray-Traced Gaming and Intelligent AI Performance on Mobile with New Arm Mali G1-Ultra GPU
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet