Open-Silicon adds Silicon Logic Engineering - for a good reason
SoC design practice has changed profoundly in recent years. While EDA vendors, IP suppliers, and the marketing departments at FPGA companies seem to think that every new SoC requires a $250 M start-from-zeros design effort, in fact SoC design has bifurcated into two distinct flows. One flow creates a platform design: a completely new SoC to serve a new application. That effort really does start from nearly scratch, and it requires an increasing wealth in people, time, and money. The other flow modifies the platform slightly to create a derivative design. The derivative flow exploits the platform as much as possible, sometimes just replacing one block in the physical design without changing the rest of the chip at all. Consequently, a derivative design may only require a dozen engineers and a couple of million dollars.
To read the full article, click here
Related Semiconductor IP
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- JPEG XL Encoder
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
Related Blogs
- The silicon behind Android
- Fab allocation back on the agenda
- Bringing MEMS and asynchronous logic into an SoC design flow
- What's happening on the 450mm wafer front?