Open-Silicon adds Silicon Logic Engineering - for a good reason
SoC design practice has changed profoundly in recent years. While EDA vendors, IP suppliers, and the marketing departments at FPGA companies seem to think that every new SoC requires a $250 M start-from-zeros design effort, in fact SoC design has bifurcated into two distinct flows. One flow creates a platform design: a completely new SoC to serve a new application. That effort really does start from nearly scratch, and it requires an increasing wealth in people, time, and money. The other flow modifies the platform slightly to create a derivative design. The derivative flow exploits the platform as much as possible, sometimes just replacing one block in the physical design without changing the rest of the chip at all. Consequently, a derivative design may only require a dozen engineers and a couple of million dollars.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related Blogs
- The silicon behind Android
- Fab allocation back on the agenda
- Bringing MEMS and asynchronous logic into an SoC design flow
- What's happening on the 450mm wafer front?
Latest Blogs
- Shaping the Future of Semiconductor Design Through Collaboration: Synopsys Wins Multiple TSMC OIP Partner of the Year Awards
- Pushing the Boundaries of Memory: What’s New with Weebit and AI
- Root of Trust: A Security Essential for Cyber Defense
- Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update
- An Introduction to AMBA CHI Chip-to-Chip (C2C) Protocol