Open-Silicon adds Silicon Logic Engineering - for a good reason
SoC design practice has changed profoundly in recent years. While EDA vendors, IP suppliers, and the marketing departments at FPGA companies seem to think that every new SoC requires a $250 M start-from-zeros design effort, in fact SoC design has bifurcated into two distinct flows. One flow creates a platform design: a completely new SoC to serve a new application. That effort really does start from nearly scratch, and it requires an increasing wealth in people, time, and money. The other flow modifies the platform slightly to create a derivative design. The derivative flow exploits the platform as much as possible, sometimes just replacing one block in the physical design without changing the rest of the chip at all. Consequently, a derivative design may only require a dozen engineers and a couple of million dollars.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related Blogs
- The silicon behind Android
- Fab allocation back on the agenda
- Bringing MEMS and asynchronous logic into an SoC design flow
- What's happening on the 450mm wafer front?
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power