Users Employ Specman Constrained-Random Verification for Complex IP
Two recent customer examples have shown the effectiveness of Specman constrained-random verification for complex SoCs. Raimund Soenning, manager of hardware development for the Graphics Competence Center at Fujitsu Semiconductor Europe (Germany), and Sarmad Dahir, ASIC designer at Ericsson (Sweden), have transitioned from traditional verification methods to a Specman-based, constrained-random, coverage-driven verification approach.
To read the full article, click here
Related Semiconductor IP
- PUF-based Post-Quantum Cryptography (PQC) Solution
- OPEN Alliance TC14 10BASE-T1S Topology Discovery IP
- HBM4 PHY IP
- 10-bit SAR ADC - XFAB XT018
- eFuse Controller IP
Related Blogs
- AI-Based Sequence Detection for IP and SoC Verification & Validation
- Industry's First Verification IP for Arm AMBA CHI-G
- Verifying CXL 3.1 Designs with Synopsys Verification IP
- Industry's First Verification IP for PCIe 7.0