Semico's SoC hierarchy. What do you do with a platypus SoC?
February 11, 2011
For the past couple of weeks, I’ve been writing about several aspects of Semico’s IP Subsystem report. (see “Are IP subsystems the next big IP category?”) The report’s premise is that the rise of IP Subsystems—IP blocks that deliver complete functions such as video or audio through a collection of design IP, software stacks, application software, and verification IP—fundamentally change the way SoCs are and will be developed in advanced process nodes. (Note: this is a concept that’s firmly embedded in the EDA360 vision.) A significant factor not yet covered in this blog is how the hierarchy of SoC definitions and metrics changes with this step up in IP complexity. This blog entry rectifies that omission.
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Bluetooth Low Energy 6.0 Scalable RF IP
- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
Related Blogs
- 70% of re-spin issues are AMS in nature: How mixed-signal design can mess up a perfectly good SoC
- Semico's list of 10 reasons why it’s taken so long for SoC design teams to adopt IP. How many apply to your team?
- ARM furthers its "cover the earth" strategy with introduction of R5 and R7 core variants for fast, real-time, deterministic SoC applications
- How many people does it take to design an SoC? - Redux. Building brains with processors.
Latest Blogs
- MIPI: Powering the Future of Connected Devices
- ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
- Designing the AI Factories: Unlocking Innovation with Intelligent IP
- Smarter SoC Design for Agile Teams and Tight Deadlines
- Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development