Semico's SoC hierarchy. What do you do with a platypus SoC?
February 11, 2011
For the past couple of weeks, I’ve been writing about several aspects of Semico’s IP Subsystem report. (see “Are IP subsystems the next big IP category?”) The report’s premise is that the rise of IP Subsystems—IP blocks that deliver complete functions such as video or audio through a collection of design IP, software stacks, application software, and verification IP—fundamentally change the way SoCs are and will be developed in advanced process nodes. (Note: this is a concept that’s firmly embedded in the EDA360 vision.) A significant factor not yet covered in this blog is how the hierarchy of SoC definitions and metrics changes with this step up in IP complexity. This blog entry rectifies that omission.
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related Blogs
- Bringing MEMS and asynchronous logic into an SoC design flow
- SoC design in China and the future for 28nm
- 70% of re-spin issues are AMS in nature: How mixed-signal design can mess up a perfectly good SoC
- Semico's list of 10 reasons why it’s taken so long for SoC design teams to adopt IP. How many apply to your team?