What's it take to design DDR4 into your next SoC? Newly released DFI 3.0 Spec opens the flood gates for DDR4 design
DDR4 SDRAM probably won’t be appearing until 2013 and probably won’t become the mainstream SDRAM technology until 2015 but the new DFI 3.0 preliminary specification from the DDR PHY Interface (DFI) Technical Group goes a long way towards making it possible for ASIC and SoC chips to incorporate DDR4 memory interfaces into their design now so that they’re ready for the future. The DFI specification defines a standard interface between a memory controller (MC) and a memory PHY and the DFI Technical Group includes representatives from ARM, Cadence, Intel, LSI, Samsung, ST-Ericsson, and Synopsys so you know there’s some weight behind this specification. By defining this standard interface, the DFI spec permits independent development of DDR MCs and PHYs, shown below, which gives SoC and Silicon Realization teams more choice.
To read the full article, click here
Related Semiconductor IP
- I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
- I2C Controller IP – Master, Parameterized FIFO, Avalon Bus
- I2C/SMBus Controller IP – Master / Slave, Parameterized FIFO, AXI/AHB/APB/Avalon Buses, SMBus Protocol
- I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
- I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
Related Blogs
- What Does It Cost You When Your SoC is Late to Market?
- How to Augment SoC Development to Conquer Your Design Hurdles
- Take your neural networks to the next level with Arm's Machine Learning Inference Advisor
- What will it take for FPGAs to become as ubiquitous as processors?