What's it take to design DDR4 into your next SoC? Newly released DFI 3.0 Spec opens the flood gates for DDR4 design
DDR4 SDRAM probably won’t be appearing until 2013 and probably won’t become the mainstream SDRAM technology until 2015 but the new DFI 3.0 preliminary specification from the DDR PHY Interface (DFI) Technical Group goes a long way towards making it possible for ASIC and SoC chips to incorporate DDR4 memory interfaces into their design now so that they’re ready for the future. The DFI specification defines a standard interface between a memory controller (MC) and a memory PHY and the DFI Technical Group includes representatives from ARM, Cadence, Intel, LSI, Samsung, ST-Ericsson, and Synopsys so you know there’s some weight behind this specification. By defining this standard interface, the DFI spec permits independent development of DDR MCs and PHYs, shown below, which gives SoC and Silicon Realization teams more choice.
To read the full article, click here
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related Blogs
- Take your neural networks to the next level with Arm's Machine Learning Inference Advisor
- What It Will Take to Build a Resilient Automotive Compute Ecosystem
- What will it take for FPGAs to become as ubiquitous as processors?
- Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?
Latest Blogs
- Rivian’s autonomy breakthrough built with Arm: the compute foundation for the rise of physical AI
- AV1 Image File Format Specification Gets an Upgrade with AVIF v1.2.0
- Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES
- Integrating Post-Quantum Cryptography (PQC) on Arty-Z7
- UA Link PCS customizations from 800GBASE-R Ethernet PCS Clause 172