Selecting optimized ESD protection for CMOS image sensors
The market for CMOS image sensors (CIS) is projected to grow with a Compound annual growth rate (CAGR) of 7 to almost 9% in the next 5 years. According to researchers it will reach a total yearly value of nearly $30B by 2026 (link 1, link 2, link 3).
CMOS imagers are used in many different markets. Consumer electronics (e.g. smartphones) represents the biggest part but the sensors are also used in surveillance and security, space, healthcare and automotive products. That last segment is actually growing faster than the total CIS market. The number of image sensors per car is increasing quickly both for viewing as for ADAS type of functionality. The total market value in automotive is projected to double from 2018 to 2024, according to Yole (link).
The technology behind CMOS imagers has seen a lot of evolution. That is needed to enable higher resolutions (number of pixels), faster capture (more frames per second), better image quality under low light settings, higher number of colors that can be recognized, and several other improvements.
The image sensors are always combined with other silicon chips like memory, compute and Artificial Intelligence (AI) devices. Some functions can be integrated on the sensor but recently 3D chip-stacking is used to integrate multiple dies in a single package.
At Sofics we have supported several companies that develop image sensors for consumer, automotive and security applications. The article below provides a summary about the 3 main aspects that IC designers need to consider when selecting the ESD protection clamps for their image sensor projects.
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