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Search (818)
Compare 818 IP from 46 vendors (1 - 10)
  • ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
    • A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
    • This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications.
    • Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications.
    Block Diagram -- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
  • High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
    • A 3.3V wirebond I/O library with 8kV HBM ESD protection, a 1.2Gbps LVDS, GPIO, and I2C compliant ODIO in an ultra-small footprint.
    • This library ensures robust reliability in challenging environments, with capabilities including 8kV HBM, 500V CDM, and a robust 2kV IEC 61000-4-2 system stress capability.
    • Its compact footprint makes it ideal for applications where size is critical.
    Block Diagram -- High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
  • Full Radiation-Hardened ESD Library in GF 12nm LP/LP+
    • Full ESD Library for Powers and I/O
    • I/O Protection 
    • Full Library is Latch-up proven to 200mA at -40C to 125C 
    • Radiation Hardened 64 MeV proton test and >1.3E+09 flux
  • ESD Cells
    • ESD structure for High-Speed analog input/output, and supply clamps
    • GlobalFoundries - 45SPCLO
  • 0.8 to 2.5GHz full wave rectifier with ESD protection
    • GF 130nm Embedded EEPROM technology process
    • Input voltage limit with up to 20mA shunt capability
    Block Diagram -- 0.8 to 2.5GHz full wave rectifier with ESD protection
  • RF ESD library in TSMC 55nm LP
    • RF ESD cells in TSMC 55nm LP targetting low-capacitance ESD protection.
    • This library is a production-quality, silicon-proven ESD library in TSMC 55nm.
    • The library does not have general ESD architecture as it is not a full I/O, but rather is a collection of standalone ESD cells that target low-capacitance RF ESD protection.
  • 6.5V ESD Clamp in 180nm Technology
    • 1.8V/5V FETs
    • 1P6M with 2fF MiMs
    • Temperature: -40C to 125C
    • Metallization for cell is M1-M5
  • 5V ESD Clamp in GlobalFoundries 180nm LPe
    • A GlobalFoundries 180nm LPe Specialized 5V ESD Clamp.
    • A key attribute of this 5V Clamp is that it can be used for either signal protection or 1.8V power supplies.
    • The clamp is a single cell, 44um x 32um in size. It is built from the substrate to metal 6.
    Block Diagram -- 5V ESD Clamp in GlobalFoundries 180nm LPe
  • ESD Protection
    • ESD Protection:
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Semiconductor IP