ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology

By Sofics

July 17, 2025

As semiconductor technology scales down, the maximum tolerated voltage by the transistors is no longer sufficiently high to accommodate (older) I/O-standards. For instance, in 4nm FinFET technology, the maximum tolerated voltage during normal operation is limited to 1.2V, which does not support common bus standards like 1.8V. As depicted in the figure below, the advancements in the technology nodes, come with a decline in the maximum supply voltage, bringing in new design challenges.

GPIO libraries contain interface options for one or more voltage domains. The maximum tolerated voltage (Vmax) is reduced for advanced CMOS and FinFET nodes. IC designers would like to use 1.8V and 3.3V interfaces even in advanced nodes to communicate with legacy chips and systems.

Moreover, due to the increased demand for high-speed communication designers have to rely on faster core devices to build the interface circuits. To allow for a safe interface between the low-voltage devices and higher voltage levels, a high voltage tolerant design concept is required.

Generic block diagram of the GPIO design with many core-side control lines for setting the drive strength, slew rate, pull-up resistors.

In this article, we present an Overvoltage tolerant (OVT) multipurpose I/O in 4nm FinFET, equipped with a driver capable of handling 1.8V signals while using only 1.2V FinFET transistors. To keep the devices within a Safe Operation Area (SOA), techniques like stacking devices and careful control of intermediate bias voltages were implemented. In this post, we will go into detail on the considerations for the design of the driver during normal operation and during an ESD event.

Transmit circuit / Driver

The IO voltage of 1.8V + 10% stays below two times the maximum tolerance of the devices. This means it is possible to use a stack of two devices when the intermediate voltage is well controlled. Just stacking 2 transistors is not enough. Both during DC and transients there could be Safe Operating Area (SOA) violations. More information about SOA issues in our earlier article.

More detailed information about the I/O circuit is available in these articles:

• I/O specs explained
• Types of overvoltage tolerant I/O
• Typical SOA violations in a stacked driver
• Overvoltage tolerant receiver structures

ESD protection of driver

ESD Design window

During an ESD-event, the control circuitry for biasing the intermediate nodes of the driver is often not (fully) functional. As a result, worst-case conditions need to be assumed in order to determine the ESD design window. In case of a stacked driver of two transistors in advanced processes, the ESD failure voltage is therefore smaller than the sum of the failure voltages of the individual devices. Even though the ESD failure voltage is not substantially larger for an OVT driver with respect to a regular driver, the minimum allowable clamping voltages (holding (V_h) and trigger (V_t1) voltages) need to be higher, in order to avoid latch-up (LU). As a result, the margin for designing an adequate ESD protection strategy drastically decreases. Consequently, this creates the need for dedicated protection strategies.

Various protection approaches can be employed to protect the I/O circuits.

• In mature processes it was common to use ‘self-protective’ drivers in the output circuit. This approach involves modifying the transistors to enhance their intrinsic ESD robustness. Specifically, the foundry proposes blocking silicide formation on the drain side of the transistors and extending the drain area. These modifications help ensure that the parasitic bipolar elements within the transistors work together effectively during an ESD event. Consequently, these self-protective transistors can also safeguard the other elements in the circuit, namely the programmable pull-up/pull-down circuit and the input/receiver circuit. In advanced processes the snapback behavior is not a given. Sometimes the transistors fail before the parasitic bipolar takes over. Extending the drain area increases the area, leakage and capacitance. Frequently, there are no proven simulation models for this layout style
• An alternative approach is to use a set of two ESD diodes (‘Dual diode approach‘) at the I/O to divert the ESD current to the power lines and the rail clamp. Since the stacked driver has a narrow ESD design window the size of the diode needs to be increased to reduce their on-resistance. The rail clamp must turn-on at a low voltage and the resistance between the I/O and rail clamp must be kept low. Sometimes IC designers will adapt the design of the I/O circuit to maximize the ESD design window.
• The third option is the ‘local clamp‘ in parallel to the I/O circuit, which was used for our 4nm I/O project and is explained further in this article.

Local ESD protection

One of the options for the ESD protection of the OVT driver is to use a local SCR-based clamp approach, in parallel to the driver circuit. The key advantages of this approach include:

• It is possible to design the functional driver circuit with minimal drain and source area, retaining the silicide, reducing area and capacitance compared to a self-protective approach where the drivers are shunting the ESD stress current.
• It is a more effective protection, shunting the ESD stress at lower voltage across the circuit compared to a dual diode approach.
• A local clamp at the I/O allows for a reduction of rail clamps in the I/O ring. As a result, this approach offers greater design flexibility. It reduces the need to keep the resistance from I/O to rail clamp low.

For this project we used the Sofics proprietary ESD-on-SCR concept which offers great protection in a small area.

Sofics proprietary ESD-on-SCR concept with (right side) and without (left side) holding diodes.

Local SCR-based clamp in FinFET technology

Two versions of the SCR-based local clamp have been implemented and compared: horizontal and vertical design. The difference is related to the orientation of the SCR compared to the FIN or gate orientation. In FinFET technology the FINs only run in one direction. In the vertical design the ESD current runs perpendicular to the FINs. In the horizontal version the ESD current runs parallel to the FIN orientation. The difference in behavior is related to which part of the junctions (sides versus bottom) are dominant. As will be obvious below the behavior of the SCR devices is very similar.

The figure presents the TLP (Transmission Line Pulse) results for both the horizontal and vertical versions of the SCR-based local clamp. During these measurements, TLP pulses with a width of 100 ns and a rise time of 10 ns were applied to the devices

TLP results of the vertical and horizontal ESD-on SCR (without holding diode) in 4nm FinFET.

Both clamps demonstrate the ability to handle TLP currents exceeding 3A. However, the vertical version is more compact, with a total area of 667.5 um² (24.756 um x 26.963 um), compared to 801.6511 um² (28.826 um x 27.81 um) for the horizontal version.

To ensure latch-up immunity, a holding diode was added to the local clamp. To examine the holding and triggering voltages, a DC current sweep was conducted, with the results shown in the figure below, for both versions at 25°C and 125°C. By adding the holding diode this ESD clamp can be safely used for 1.8V I/Os.

The Voltage sweep DC measurement of ESD-on SCR with a holding diode. For Latch-up immunity we look at the DC holding voltage at high temperature.

The plot below shows the results of the Very Fast TLP measurement where fast and short pulses were applied between I/O and VSS and between VDD and I/O. Both horizontal and vertical layouts surpass 6A of VF-TLP stress.

VF-TLP results of the vertical and horizontal ESD-on SCR with holding diode in 4nm FinFET technology.

The table below provides a summary of the leakage and capacitance information for both cases. The parasitic capacitance simulations were derived from junction capacitance using foundry-supplied SPICE models, while metallization capacitance was obtained through PEX extraction. The leakage was measured at room temperature and at 125°C.

Conclusion

This work presents a design of a 1.8V driver using 1.2V transistors in 4nm FinFET technology, addressing key challenges in maintaining reliability and scalability of such structures. A notable challenge of the design lies in the pad voltage which is beyond the maximum voltage of the I/O transistors. To overcome this constrain, the design requires stacked transistors, impedance control elements and complex biasing strategies to ensure robustness.

Due to the small design margins the ESD-on structures had to be specially designed to meet the harsh conditions. A local ESD protection approach using SCR devices is used. Horizontal and vertical SCRs are compared, demonstrating the differences in terms of area efficiency, in triggering and holding voltages. The addition of a holding diode to the ESD-on-SCR ensures latch-up immunity, making this approach highly reliable for advanced I/O circuits.