5V I/O and ESD in TSMC 12nm FFC/FFC+

Overview

A 5V Library for Generic I/O and ESD Applications TSMC 12NM FFC/FFC+ process.

This library is a base set of ESD protection structures for I/O and Power supplies. The design targets up to 8A applications (>8kV HBM). The I/Os are designed to trigger and protect interfaces during Electrical Overstress (EOS) events during normal operation.

 Models and Support Files

  •  GDS Layouts
  •  OA Database
  •   CDL and Spectre netlist for simulation and LVS

Front-end Devices

  •  1.8V FETs only, No ESD implant layer or special masks required.
  •  Back-end: Up to Metal 4.

Key Features

  •   Power Clamp footprint is 35um x 135um
  •   I/O footprint is 20um x 20um
  •   AVDD = up to 5V
  •   Capacitance 150fF to 250fF including bond pads*
  •   HBM >8kV*, CDM >800V*, IEC >2kV option*
  •   EOS Protection
  •   Junction temperature range: -40C to 125C

Technical Specifications

Foundry, Node
TSMC 12nm FFC/FFC+
TSMC
In Production: 12nm
Pre-Silicon: 12nm
Silicon Proven: 12nm
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Semiconductor IP