Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700

By Don Smith, MIPS

November 14, 2024

Do you need more compute elements? Do you need more memory? Do you need more cache? Last week we announced the MIPS P8700, the industry’s first AI-enabled RISC-V automotive CPU for ADAS and autonomous vehicles. The MIPS P8700 gives you the freedom to choose how to solve your problem.

How is scalability optimized?

The MIPS P8700 scalability starts with the core. Your core can choose one or two high performance, out-of-order compute engines known as harts within a single core. That same core can choose 32KB or 64KB L1 instruction cache and 32KB or 64KB L1 data cache for the two harts to share.

You can further enhance the core with L2 cache from 256KB to 2MB. At this L2 level you can also keep building with multiple cores in a single cluster. Add up to 5 more cores to give a cluster of 6 cores and 12 harts of compute with a shared L2 cache.

To read the full article, click here