RISC-V Chiplets, Disaggregated Die, and Tiles
Scalable High-Performance Computing SoC Design with RISC-V
Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules, a growing trend among SoC designers is making the interposer act like a ‘mainboard’ to host multiple chips. Together, these chips form a coherent whole product intended for a specific market and offer both advanced workload performance and efficiency benefits.
The technology industry is shifting to custom designs, replacing traditional general-purpose CPU and discrete accelerator platforms. Instead, the computing platform can implement application-specific processing requirements at many levels, down to the instruction set architecture (ISA). Enabling this industry shift is central to SiFive’s mission and why SiFive’s founders invented RISC-V a decade ago.
To read the full article, click here
Related Semiconductor IP
- All-In-One RISC-V NPU
- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
- RISC-V CPU IP
- Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
- 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
Related Blogs
- Effectively hiding sensitive data with RISC-V Zk and custom instructions
- RISC-V Impact on Technology and Innovation
- Synopsys and Alchip Collaborate to Streamline the Path to Multi-die Success with Soft Chiplets
- Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich
Latest Blogs
- Securing The Road Ahead: MACsec Compliant For Automotive Use
- Beyond design automation: How we manage processor IP variants with Codasip Studio
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
- The Role of GPU in AI: Tech Impact & Imagination Technologies
- Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding